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adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz rev. 03 ? 2 july 2012 product data sheet 1. general description the adc1006s055/070 are a family of bipolar cmos (bicmos ) 10-bit analog-to-digital co nverters (adc) optimized for a wide range of applications such as cellular infrastructures, professional telecommunications, imaging, and digital radio. it converts the analog input signal into 10-bit binary coded digital words at a maximum sampling rate of 70 mhz. all static digital inputs (sh, ce and otc) are transistor-transistor logic (ttl) and cmos compatible and all outputs are cmos compatible. a sine wave clock input signal can also be used. 2. features ? 10-bit resolution ? sa mpling rate up to 70 mhz ? ? 3 db bandwidth of 245 mhz ? 5 v power supplies and 3.3 v output power supply ? bina ry or two?s complement cmos outputs ? in- range cmos compatible output ? ttl and cmos compatible static digital inputs ? tt l and cmos compatible digital outputs ? dif ferential ac or positive emitter-coupled logic (pecl) clock input; ttl compatible ? powe r dissipation 550 mw (typical) ? l ow analog input capacitance (typical 2 pf), no buffer amplifier required ? in tegrated sample-a nd-hold amplifier ? dif ferential analog input ? exte rnal amplitude range control ? v oltage controlled regulator included ? ? 40 ? c t o +85 ? c a mbient temperature 3. applications high-speed analog-to-digital conversion for: ? cellular infrastruc ture ? pr ofessional telecommunication ? digit al radio ? radar ? medical imaging ? fixed network ? ca ble modem
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 2 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz ? barcode scanner ? ca ble modem termination system (cmts) /data over cable service interface specification (docsis) 4. quick reference data table 1. quick reference data v cca = v2 to v44, v3 to v4 and v41 to v40 = 4.75 v to 5.25 v; v ccd = v37 to v38 and v15 to v17 = 4.75 v to 5.25 v; v cco = v33 to v34 = 3.0 v to 3.6 v; agnd and dgnd shorted to gether; t amb = ? 40 ? c to +85 ? c; v i(in)(p-p) ? v i(inn)(p-p) = 1.9 v; v vref = v cca3 ? 1.75 v; v i(cm) = v cca3 ? 1.6 v; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, t amb = 25 ? c and c l = 10 pf; unless otherwise specified. symbol parameter conditions min typ max unit v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 3.6 v i cca analog supply current - 78 87 ma i ccd digital supply current - 27 30 ma i cco output supply current f clk = 20 mhz; f i = 400 khz - 3 4 ma inl integral non-linearity f clk = 20 mhz; f i = 400 khz - ? 0.65 ? 1.12 lsb dnl differential non-linearity f clk = 20 mhz; f i = 400 khz (no missing code gu aranteed) - ? 0.12 ? 0.27 lsb f clk(max) maximum clock frequency adc1006s055h 55 - - mhz adc1006s070h 70 - - mhz p tot total power dissipation f clk = 55 mhz; f i = 20 mhz - 550 660 mw 5. ordering information table 2. ordering information type number package sampling frequency (mhz) name description version adc1006s055h qfp44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 ? 10 ? 1.75 mm sot307-2 55 adc1006s070h qfp44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 ? 10 ? 1.75 mm sot307-2 70
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 3 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 6. block diagram 014aaa464 msb data outputs 19 d9 d8 d7 d6 d5 d4 d3 43 42 39 1 5 11 12 vref fsref sh dec cmadc 6 to 10, 13, 14, 16, 31, 32 n.c. d2 21 22 23 24 25 26 27 28 29 30 d1 d0 lsb v cco 33 ir 34 20 18 cmos outputs latches analog-to-digital converter clock driver 15 v ccd2 37 v ccd1 41 v cca4 3 v cca3 2 v cca1 36 clk 35 clkn cmos output ognd overflow/ underflow latch vref reference cmadc reference ce otc adc1006s055/070 17 dgnd2 38 dgnd1 40 agnd4 4 agnd3 44 agnd1 inn in amp s sample - and - hold fig 1. block diagram
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 4 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 7. pinning information 7.1 pinning adc1006s055/070 cmadc v cco v cca1 n.c. v cca3 n.c. agnd3 d0 dec d1 n.c. d2 n.c. d3 n.c. d4 n.c. d5 n.c. d6 vref d7 fsref agnd1 n.c. inn n.c. in v ccd2 v cca4 n.c. agnd4 dgnd2 sh otc dgnd1 ce v ccd1 ir clk d9 clkn d8 ognd 014aaa442 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 fig 2. pin configuration 7.2 pin description table 3. pin description symbol pin description cmadc 1 regulator output common mode adc input v cca1 2 analog supply voltage 1 (5 v) v cca3 3 analog supply voltage 3 (5 v) agnd3 4 analog ground 3 dec 5 decoupling node n.c. 6 not connected n.c. 7 not connected n.c. 8 not connected n.c. 9 not connected n.c. 10 not connected vref 11 reference voltage input fsref 12 full-scale reference output n.c. 13 not connected n.c. 14 not connected v ccd2 15 digital supply voltage 2 (5 v) n.c. 16 not connected dgnd2 17 digital ground 2
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 5 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 8. limiting values otc 18 control input two?s complement output; active high ce 19 chip enable input (cmos level; active low) ir 20 in-range output d9 21 data output; bit 9 (most significant bit (msb)) d8 22 data output; bit 8 d7 23 data output; bit 7 d6 24 data output; bit 6 d5 25 data output; bit 5 d4 26 data output; bit 4 d3 27 data output; bit 3 d2 28 data output; bit 2 d1 29 data output; bit 1 d0 30 data output; bit 0 (least significant bit (lsb)) n.c. 31 not connected n.c. 32 not connected v cco 33 output supply voltage (3.3 v) ognd 34 output ground clkn 35 complementary clock input clk 36 clock input v ccd1 37 digital supply voltage 1 (5 v) dgnd1 38 digital ground 1 sh 39 sample-and-hold enable input (cmos level; active high) agnd4 40 analog ground 4 v cca4 41 analog supply voltage 4 (5 v) in 42 analog input voltage inn 43 complementary analog input voltage agnd1 44 analog ground 1 table 3. pin description ?continued symbol pin description table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v cca analog supply voltage [1] 0.3 +7.0 v v ccd digital supply voltage [1] 0.3 +7.0 v v cco output supply voltage [1] 0.3 +7.0 v ' v cc supply voltage difference v cca v ccd 1.0 +1.0 v v ccd v cco 1.0 +4.0 v v cca v cco 1.0 +4.0 v v i(in) input voltage on pin in referenced to agnd 0.3 v cca v v i(inn) input voltage on pin inn 0.3 v cca v
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 6 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz [1] the supply voltages v cca , v ccd and v cco may have any value between ?0.3 v and +7.0 v provided that the supply volt age differences ? v cc are respected. 9. thermal characteristics table 5. thermal characteristics symbol parameter condition value unit r th(j-a) thermal resistance from junction to ambient in free air 75 k/w 10. characteristics v i(clk)(p-p) peak-to-peak clock input voltage differential clock d rive at pins 35 and 36 - v ccd v i o output current - 10 ma t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 40 +85 ?c t j junction temperature - 150 ?c table 4. limiting values ?continued in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit table 6. characteristics v cca = v2 to v44, v3 to v4 and v41 to v40 = 4.75 v to 5.25 v; v ccd = v37 to v38 and v15 to v17 = 4.75 v to 5.25 v; v cco = v33 to v34 = 3.0 v to 3.6 v; agnd and dgnd shorted together; t amb = ? 40 ? c to +85 ? c; v i(in)(p-p) ? v i(inn)(p-p) = 1.9 v; v vref = v cca3 ? 1.75 v; v i(cm) = v cca3 ? 1.6 v; typical values measured at v cca = v ccd = 5 v an d v cco = 3.3 v, t amb = 25 ? c and c l = 10 pf; unless otherwise specified. symbol parameter conditions test [1] min typ max unit supplies v cca analog supply voltage 4.75 5.0 5.25 v v ccd digital supply voltage 4.75 5.0 5.25 v v cco output supply voltage 3.0 3.3 3.6 v i cca analog supply current i - 78 87 ma i ccd digital supply current i - 27 30 ma i cco output supply current f clk = 20 mhz; f i = 400 khz i - 3 4 ma f clk = 55 mhz; f i = 20 mhz i - 9.5 12 ma p tot total power dissipation f clk = 55 mhz; f i = 20 mhz - 550 660 mw inputs clk and clkn (referenced to dgnd) [2] v il low-level input voltage pecl mode; v ccd = 5 v i 3.19 - 3.52 v ttl mode c 0 - 0.8 v
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 7 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz v ih high-level input voltage pecl mode; v ccd = 5 v i 3.83 - 4.12 v ttl mode c 2.0 - v ccd v i il low-level input current v clk or v clkn = 3.19 v c 10 - - p a i ih high-level input current v clk or v clkn = 3.83 v c - - 10 p a v i(dif)(p-p) peak-to-peak differential input voltage ac driving mode; dc voltage level = 2.5 v c 1 1.5 2.0 v r i input resistance f clk = 55 mhz d 2 - - k : c i input capacitance f clk = 55 mhz d - - 2 pf otc, sh and ce (referenced to dgnd); see table 7 and 8 v il low-level input voltage i 0 - 0.8 v v ih high-level input voltage i 2.0 - v ccd v i il low-level input current v il = 0.8 v i 20 - - p a i ih high-level input current v ih = 2.0 v i - - 20 p a in and inn (referenced to agnd); see table 7, v vref = v cca3 1.75 v i il low-level input current sh = high c - 10 - p a i ih high-level input current sh = high c - 10 - p a r i input resistance f i = 20 mhz d - 14 - m : c i input capacitance f i = 20 mhz d - 450 - ff v i(cm) common-mode input voltage v i(in) = v i(inn) output code 512 c v cca3 1.7 v cca3 1.6 v cca3 1.2 v voltage controlled regulator output cmadc v o(cm) common-mode output voltage i - v cca3 1.6 - v i load load current i - 1 2 ma voltage input v ref [3] v ref reference voltage full-scale fixed voltage; f i = 20 mhz; f clk = 55 mhz c - v cca3 1.75 - v i ref reference current c - 0.3 10 p a v i(dif)(p-p) peak-to-peak differential input voltage v i(in)(p-p) v i(inn)(p-p) ; v ref = v cca3 1.75 v; v i(cm) = v cca3 1.6 v c - 1.9 - v table 6. characteristics ?continued v cca = v2 to v44, v3 to v4 and v41 to v40 = 4.75 v to 5.25 v; v ccd = v37 to v38 and v15 to v17 = 4.75 v to 5.25 v; v cco = v33 to v34 = 3.0 v to 3.6 v; agnd and dgnd shorted together; t amb = 40 q c to +85 q c; v i(in)(p-p) v i(inn)(p-p) = 1.9 v; v vref = v cca3 1.75 v; v i(cm) = v cca3 1.6 v; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions test [1] min typ max unit
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 8 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz voltage controlled regulator output fsref v o(ref) reference output voltage v i(in)(p-p) v i(inn)(p-p) = 1.9 v i - v cca3 1.75 - v digital outputs d9 to d0 and ir (referenced to ognd) v ol low-level output voltage i ol = 2 ma i 0 - 0.5 v v oh high-level output voltage i oh = 0.4 ma i v cco 0.5 - v cco v i o output current 3-state output level between 0.5 v and v cco i 20 - +20 p a switching characteristics; clock frequency f clk ; see figure 3 f clk(min) minimum clock frequency sh = high c - - 7 mhz f clk(max) maximum clock frequency adc1006s055h i 55 - - mhz adc1006s070h c 70 - - mhz t w(clk)h high clock pulse width f i = 20 mhz c 6.8 - - ns t w(clk)l low clock pulse width f i = 20 mhz c 6.8 - - ns analog signal processing; 50 % clock duty factor; v i(in)(p-p) v i(inn)(p-p) = 1.9 v; v vref = v cca3 1.75 v; see table 7 linearity inl integral non-linearity f clk = 20 mhz; f i = 400 khz i - r 0.65 r 1.12 lsb dnl differential non-linearity f clk = 20 mhz; f i = 400 khz (no missing code guaranteed) i - r 0.12 r 0.27 lsb e offset offset error v cca = v ccd = 5 v; v cco = 3.3 v; t amb = 25 q c; output code = 512 c 25 +5 +25 mv e g gain error spread from device to device; v cca = v ccd = 5 v; v cco = 3.3 v; t amb = 25 q c c 7 - +7 %fs bandwidth (f clk = 55 mhz) [4] b bandwidth 3 db; full-scale input c 220 245 - mhz table 6. characteristics ?continued v cca = v2 to v44, v3 to v4 and v41 to v40 = 4.75 v to 5.25 v; v ccd = v37 to v38 and v15 to v17 = 4.75 v to 5.25 v; v cco = v33 to v34 = 3.0 v to 3.6 v; agnd and dgnd shorted together; t amb = 40 q c to +85 q c; v i(in)(p-p) v i(inn)(p-p) = 1.9 v; v vref = v cca3 1.75 v; v i(cm) = v cca3 1.6 v; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions test [1] min typ max unit
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 9 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz harmonics d 2h second harmonic level adc1006s055h (f clk = 55 mhz) f i = 4.43 mhz c - 77 - dbfs f i = 10 mhz c - 76 - dbfs f i = 15 mhz c - 75 - dbfs f i = 20 mhz i - 73 - dbfs adc1006s070h (f clk = 70 mhz) f i = 4.43 mhz c - 75 - dbfs f i = 10 mhz c - 74 - dbfs f i = 15 mhz c - 70 - dbfs d 3h third harmonic level adc1006s055h (f clk = 55 mhz) f i = 4.43 mhz c - 73 - dbfs f i = 10 mhz c - 73 - dbfs f i = 15 mhz c - 73 - dbfs f i = 20 mhz i - 72 - dbfs adc1006s070h (f clk = 70 mhz) f i = 4.43 mhz c - 73 - dbfs f i = 10 mhz c - 73 - dbfs f i = 15 mhz c - 72 - dbfs total harmonic distortion [5] thd total harmonic distortion adc1006s055h (f clk = 55 mhz) f i = 4.43 mhz c - 68 - dbfs f i = 10 mhz c - 68 - dbfs f i = 15 mhz c - 68 - dbfs f i = 20 mhz i - 68 - dbfs adc1006s070h (f clk = 70 mhz) f i = 4.43 mhz c - 67 - dbfs f i = 10 mhz c - 67 - dbfs f i = 15 mhz c - 66 - dbfs thermal noise n th(rms) rms thermal noise shorted input; sh = high; f clk = 55 mhz c - 0.12 - lsb table 6. characteristics ?continued v cca = v2 to v44, v3 to v4 and v41 to v40 = 4.75 v to 5.25 v; v ccd = v37 to v38 and v15 to v17 = 4.75 v to 5.25 v; v cco = v33 to v34 = 3.0 v to 3.6 v; agnd and dgnd shorted together; t amb = 40 q c to +85 q c; v i(in)(p-p) v i(inn)(p-p) = 1.9 v; v vref = v cca3 1.75 v; v i(cm) = v cca3 1.6 v; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions test [1] min typ max unit
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 10 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz signal-to-noise ratio [6] s/n signal-to-noise ratio adc1006s055h (f clk = 55 mhz) f i = 4.43 mhz c - 60 - dbfs f i = 10 mhz c - 60 - dbfs f i = 15 mhz c - 60 - dbfs f i = 20 mhz i - 59.5 - dbfs adc1006s070h (f clk = 70 mhz) f i = 4.43 mhz c - 60 - dbfs f i = 10 mhz c - 60 - dbfs f i = 15 mhz c - 59 - dbfs spurious free dynamic range; see figure 7, 13 and 14 sfdr spurious free dynamic range adc1006s055h (f clk = 55 mhz) f i = 4.43 mhz c - 71 - dbfs f i = 10 mhz c - 70 - dbfs f i = 15 mhz c - 70 - dbfs f i = 20 mhz i - 70 - dbfs adc1006s070h (f clk = 70 mhz) f i = 4.43 mhz c - 70 - dbfs f i = 10 mhz c - 69 - dbfs f i = 15 mhz c - 68 - dbfs effective number of bits [7] enob effective number of bits adc1006s055h (f clk = 55 mhz) f i = 4.43 mhz c - 9.5 - bit f i = 10 mhz c - 9.5 - bit f i = 15 mhz c - 9.5 - bit f i = 20 mhz i - 9.5 - bit adc1006s070h (f clk = 70 mhz) f i = 4.43 mhz c - 9.5 - bit f i = 10 mhz c - 9.5 - bit f i = 15 mhz c - 9.4 - bit intermodulation; (f clk = 55 mhz; f i = 20 mhz) [8] d im intermodulation suppression c - 69 - dbfs imd3 third-order intermodulation distortion c - 79 - dbfs bit error rate (f clk = 55 mhz) ber bit error rate f i = 20 mhz; v i = r 16 lsb at code 512 c - 10 14 - times/ sample table 6. characteristics ?continued v cca = v2 to v44, v3 to v4 and v41 to v40 = 4.75 v to 5.25 v; v ccd = v37 to v38 and v15 to v17 = 4.75 v to 5.25 v; v cco = v33 to v34 = 3.0 v to 3.6 v; agnd and dgnd shorted together; t amb = 40 q c to +85 q c; v i(in)(p-p) v i(inn)(p-p) = 1.9 v; v vref = v cca3 1.75 v; v i(cm) = v cca3 1.6 v; typical values measured at v cca = v ccd = 5 v and v cco = 3.3 v, t amb = 25 q c and c l = 10 pf; unless otherwise specified. symbol parameter conditions test [1] min typ max unit
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 11 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz [1] d = guaranteed by design; c = guaranteed by c haracterization; i = 100 % industrially tested. [2] the circuit has two clock inputs: clk and clkn. there are 5 modes of operation: a) pecl mode 1: (dc level vary 1 : 1 with v ccd ) clk and clkn inputs are at differential pecl levels. b) pecl mode 2: (dc level vary 1 : 1 with v ccd ) clk input is at pecl level and sampling is taken on the falling edge of the clock input signal. a dc level of 3.65 v has to be applied on clkn decoupled to gnd via a 100 nf capacitor. c) pecl mode 3: (dc level vary 1 : 1 with v ccd ) clkn input is at pecl level and sampling is taken on the rising edge of the clock input signal. a dc level of 3.65 v has to be applied on clk decoupled to gnd via a 100 nf capacitor. d) differential ac driving mode 4: when driving the clk input directly and with any ac signal of minimum 1 v (p-p) and with a dc level of 2.5 v, the sampling takes place at the falling edge of the clock signa l. when driving the clkn input with the same signal, sampling takes place at the rising edge of the clock signal. it is re commended to decouple the clkn or clk input to dgnd via a 100 nf cap acitor. e) ttl mode 1: clk input is at ttl level and sampling is taken on the fal ling edge of the clock input signal. in that case clkn pin has to be connected to the ground. [3] the adc input range can be adjusted with an externa l reference connected to vref pin. this voltage has to be referenced to v cca ; see figure 12. [4] the ?3 db analog bandwidth is determined by the 3 db reduction in the reconstructed output, the input be ing a full-scale sine wave. [5] total harmonic distortion (t hd) is obt ained with the addition of the first five harmonics: thd 20 log ? 2h ?? 2 ? 3h ?? 2 ? 4h ?? 2 ? ?? 2 ? 6h ?? 2 ++++ a 1h ?? 2 -------------------------------------------------------------------------------------------------------------------------------------- = where ? 1h is the fundamental harmonic referenced at 0 db for a full-scale sine wave input; see figure 6. [6] signal-to-noise ratio (s/n) takes into account all harmo n ics above five and noise up to nyquist frequency; see figure 8. [7] effective number of bits are obtained via a fast fourier transform (fft). the calculation takes into account all harmonics and noise up to half of the clock frequency (nyquist frequency). conversion to signal-to_noi se_distortion ratio (sinad) is given by sinad = enob ? 6.02 + 1.76 db; see figure 5. [8] intermodulation measured relative to ei ther tone with analog input frequencies of 20 mhz and 20.1 mhz. the two input signals have the same amplitude and the total amplitude of both signal s provides full-scale to the converter ( ?6 db below full scale for each input signal). ? imd3 is the ratio of the rms value of either input tone to t he rms value of the worst case third order intermodulation product. [9] output data acquisition: the output data is available af ter the maximum delay of t d(o) ; see figure 3. timing (c l = 10 pf) [9] t d(s) sampling delay time c - 0.25 1 ns t h(o) output hold time c 4 6.4 - ns t d(o) output delay time c - 9.0 13 ns 3-state output delay times; see figure 4 t dzh float to active high delay time c - 5.1 9.0 ns t dzl float to active low delay time c - 7.0 11 ns t dhz active high to float delay time c - 9.7 14 ns t dlz active low to float delay time c - 9.5 13 ns table 6. characteristics ?continued v cca = v2 to v44, v3 to v4 and v41 to v40 = 4.75 v to 5.25 v; v ccd = v37 to v38 and v15 to v17 = 4.75 v to 5.25 v; v cco = v33 to v34 = 3.0 v to 3.6 v; agnd and dgnd shorted together; t amb = ? ? ? ? ? ? ? symbol parameter conditions test [1] min typ max unit
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 12 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 11. additional information relating to table 6 table 7. output coding with differential inputs (typical values to agnd); v i(in)(p-p) ? v i(inn)(p-p) = 1.9 v, v vref = v cca3 ? 1.75 v code v i(a)(p-p) (v) v i(a)(p-p) (v) ir binary outputs d9 to d0 two?s complement outputs [1] d9 to d0 underflow < 3.125 > 4.075 0 00 0000 0000 10 0000 0000 0 3.125 4.075 1 00 0000 0000 10 0000 0000 1 - - 1 00 0000 0001 10 0000 0001 ? - - ? ? ? 511 3.6 3.6 1 01 1111 1111 11 1111 1111 ? - - ? ? ? 1022 - - 1 11 1111 1110 01 1111 1110 1023 4.075 3.125 1 11 1111 1111 01 1111 1111 overflow > 4.075 < 3.125 0 11 1111 1111 01 1111 1111 [1] two?s complement reference is inverted msb. table 8. mode selection otc ce d0 to d9 and ir 0 0 binary; active 1 0 two?s complement; active x [1] 1 high-impedance [1] x = don?t care. table 9. sample-and-hold selection sh sample-and-hold 1 active 0 inactive; tracking mode
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 13 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz sample n + 1 sample n clk 014aaa465 sample n + 2 sample n + 1 sample n sample n + 2 t w(clk)l t w(clk)h data d0 to d9 high 50 % lo w high 50 % low in t d(s) t h(o) t d(o) data n ? 2 data n ? 1 data n data n + 1 fig 3. timing diagram 014aaa443 50 % 50 % high low t dzh t dhz 50 % high low t dzl t dlz 10 % 90 % output data v ccd output data 3.3 k 15 pf s1 v cco adc1006s 070 ce test t dlz t dzl t dhz s1 v cco v cco ognd ognd t dzh 0 v ce (1) frequency on pin ce = 100 khz. fig 4. timing diagram and test condit ions of 3-state output delay time
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 14 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz f i (mhz) 025 20 10 15 5 014aaa444 9.50 9.40 9.60 9.70 enob (bit) 9.30 (1) (2) f i (mhz) 025 20 10 15 5 014aaa445 ?67 ?69 ?65 ?63 thd (db) ?71 (1) (2) (1) 55 mhz. (2) 70 mhz. (1) 55 mhz. (2) 70 mhz. fig 5. effective number of bits (enob) as a function of input frequency (sample device) fig 6. total harmonic distortion (thd) as a function of in put frequency (sample device) f i (mhz) 025 20 10 15 5 014aaa446 70 71 69 72 73 sfdr (db) 68 (1) (2) f i (mhz) 025 20 10 15 5 014aaa447 59.4 59.6 59.2 59.8 60.0 s/n (db) 59.0 (1) (2) (1) 55 mhz. (2) 70 mhz. (1) 55 mhz. (2) 70 mhz. fig 7. spurious free dynamic range (sfdr) as a function of input fr equency (sample device) fig 8. signal-to-noise ratio (s/n) as a funct ion of input frequency (sample device)
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 15 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 014aaa448 ?80 ?120 ?40 0 power spectrum (db) ?160 f i (mhz) 0 30 20 10 5 25 15 fig 9. single-tone; f i = 20 mhz; f clk = 55 mhz 014aaa449 ?80 ?120 ?40 0 power spectrum (db) ?160 f i (mhz) 0 30 20 10 5 25 15 fig 10. two-tone; f i 1 = 20 mhz; f i 2 = 20.1 mhz; f clk = 55 mhz
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 16 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz output code 0 1024 768 512 256 014aaa450 ?0.60 0.60 0.20 ?0.20 1.00 output range (inl) fig 11. integral non-linearity (inl) output code 0 1024 768 512 256 014aaa451 0 0.10 ?0.10 0.20 0.30 dnl (lsb) ?0.20 fig 12. differential non-linearity (dnl)
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 17 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz input amplitude (dbfs) ?60 0 ?20 ?10 ?30 ?50 ?40 014aaa452 40 60 80 sfdr (dbfs) 20 (1) (2) (3) (1) f i = 4.43 mhz. (2) f i = 20 mhz. (3) sfdr = 80 db. fig 13. sfdr as a function of input amplitude; v i(in)(p-p) ? v i(inn)(p-p) = 1.9 v; f clk = 40 mhz input amplitude (dbfs) ?60 0 ?20 ?10 ?30 ?50 ?40 014aaa453 40 60 80 sfdr (dbfs) 20 (1) (2) (3) (1) f i = 4.43 mhz. (2) f i = 20 mhz. (3) sfdr = 80 db. fig 14. sfdr as a function of input amplitude; v i(in)(p-p) ? v i(inn)(p-p) = 1.9 v; f clk = 55 mhz
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 18 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz v cca ? v vref (v) 1.3 2.2 2.0 2.1 1.81.7 1.9 1.5 1.6 1.4 014aaa455 55 45 65 75 50 40 60 70 (db) 35 8.0 7.0 9.0 10.0 7.5 6.5 8.5 9.5 (bit) 6.0 (1) (2) (3) 014aaa456 v cca ? v vref (v) 1.3 2.2 2.0 2.1 1.81.7 1.9 1.5 1.6 1.4 1.8 1.4 2.2 2.6 1.0 v i(in)(p-p) ? v i(inn)(p-p) (v) (1) sfdr. (2) enob. (3) s/n. fig 15. sfdr, enob and s/n as a function of v cca ? v vref ; f clk = 55 mhz; f i = 20 mhz fig 16. adc full-scale; v i(in)(p-p) ? v i(inn)(p-p) as a function of v cca ? v vref
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 19 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 12. application information 12.1 application diagrams 014aaa457 100 100 100 nf 100 nf 5 v 100 nf 100 nf 100 nf 220 nf 10 nf 5 v in 1 : 1 inn 5 v 100 nf 5 v 5 v sh mode clk n.c. n.c. d0 (lsb) adc1006s055/070 d1 d2 d3 d4 d5 d6 n.c. n.c. n.c. n.c. n.c. d7 d8 chip select input ir n.c. n.c. n.c. output format select d9 (msb) vref 343536 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 3738394041424344 2221201918171615141312 the analog, digital and output suppl ies should be separated and decoupled. fig 17. application diagram 014aaa458 270 270 clkn clk ttl input mc100 elt20 pecl d fig 18. application diagram for differential clock input pecl compatible using a ttl to pecl translator
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 20 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 014aaa459 adc1006s 055/070 clkn clk ttl input fig 19. application diagram for ttl single-ended clock
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 21 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 12.2 demonstration board ic2 adc1006s055/070 014aaa460 34 35 36 37 38 39 40 41 42 43 44 ognd clkn clk v ccd1 dgnd1 sh agnd4 v cca4 in inn agnd1 v cca v ccd v cca v cc v cco v cc 22 21 20 19 18 17 16 15 14 13 12 cmadc v cca1 v cc v cca v cc v cca v cc v cco v cco v cca3 agdn3 dec n.c. n.c. n.c. n.c. n.c. vref 33 32 31 30 29 28 27 26 25 24 23 1234567891011 v cco n.c n.c d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 ir ce otc dgnd2 n.c. v ccd2 n.c. n.c. fsref mc78mo5cdt in out ici gnd 2 1 4 3 6 5 8 7 10 9 12 11 14 13 16 15 18 17 20 19 22 21 24 b8 23 b11 r4 50 r3 100 fl3 fl1 fl2 c13 100 nf c6 330 nf c15 10 nf r1 100 5 k fl4 c8 10 nf c17 10 nf c19 c1 22 f (20 v) c2 4.7 f (16 v) c3 1 f t1 tp2 tm3 r5 4.7 k c4 1 f r2 62 r6 2.4 k 1 k s2 s4 s3 b7 b5 1.2 k c11 100 nf c18 10 nf c5 330 nf c12 100 nf c16 10 nf c10 100 nf pmbt 2222a d2 bzv55c3v6 c14 100 nf c7 330 nf s1 s5 r9 100 j2 j3 j1 j4 j4 1 2 byd17g d3 clk2 clk1 clk1 in c9 220 nf p1 mclt1_6t_kk81 tr1 cmadc 12 v 1 3 gnd r8 750 d1 lgt679 330 nf p2 r7 c8 is close to tr1 pin. fig 20. demonstration board schematic
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 22 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 014aaa466 j4 c4 c5 d2 tp2 p2 c3 d3 r2 r5 r7 r4 r6 c11 c10 c14 p1 r1 r3 j3 j2 j1 1 1 1 1 1 1 12 23 34 c12 s2 s5 s1 s3 s4 b7 b4 b5 b8 b11 c7 c9 r9 fl4 fl2 t1 tm3 tm2 tm1 c2 c1 ic1 ic2 tr1 r8 d1 12 fig 21. component placement (top side) 014aaa467 c6 fl1 fl3 c8 c13 c17 c15 c19 c16 c18 fig 22. component placement (underside)
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 23 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 014aaa461 1 fig 23. printed-circuit board layout (top layer) 014aaa462 2 fig 24. printed-circuit board layout (ground layer)
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 24 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 014aaa463 3 fig 25. printed-circuit board layout (power plane) 12.3 alternative parts the following alternative parts are also available: table 10. alternative parts type number description sampling frequency ADC1206S040 single 12 bits adc [1] 40 mhz adc1206s055 single 12 bits adc [1] 55 mhz adc1206s070 single 12 bits adc [1] 70 mhz [1] pin to pin compatible 12.4 recommended companion chip the recommended companion chip is the tda9901 wideband differential digital controlled variable gain amplifier.
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 25 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 13. support information 13.1 definitions 13.1.1 non-linearities 13.1.1.1 integral non-linearity (inl) it is defined as the deviation of the transfer fu nction from a best fit straight line (linear regression computation). the inl of the code i is obtained from the equation: inl i ?? v i i ?? v i ideal ?? ? s ----------------------------------------- - = (1) where i02 n 1 ? ?? ? = and s = slope of the ideal straight line = code width; i = code value. 13.1.1.2 differential non-linearity (dnl) it is the deviation in code width from the value of 1 lsb. dnl i ?? v i i1 + ?? v i i ?? ? s --------------------------------------- 1 ? = (2) where i02 n 2 ? ?? ? = 13.1.2 dynamic parameters (single tone) figure 26 shows the spectrum of a full-scale in put sine wave with frequency f t , conforming to coherent sampling (f t / f s = m / n, where m is the number of cycles and n is number of samples, m and n being relatively prime), and digitized by the adc under test. a 2 a 3 a k a 1 sfdr 014aaa440 f s /2 measured output range (mhz) magnitude fig 26. spectrum of full-scale input sine wave with frequency f t
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 26 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz remark: in the following equations, p noise is the power of the terms which include the effects of random noise, non-linearities, sampling time errors, and ?quantization noise?. 13.1.2.1 signal-to-noise and dis tortion (sinad) the ratio of the output signal power to the noi se a nd distortion power for a given sample rate and input frequency, excluding the dc component: sinad db ?? 10 p signal p noise distortion + ------------------------------------------ log = (3) 13.1.2.2 effective number of bits (enob) it is derived from sinad and gives the theoretical resolution an ideal adc would require to ob tain the same sinad measured on t he real adc. a good approximation gives: enob sinad db ?? 1.76 ?? ? ?? 6.02 ?? ? = 13.1.2.3 total harmonic distortion (thd) the ratio of the power of the harmonics to the power of the fundamental. for k-1 h armonics the thd is: thd db ?? 10 = p harmonics p signal -------------------------- - log (4) where p harmonics ? 2 2 ? 3 2 ? k 2 ++ = and p signal ? 1 2 = the value of k is usually 6 (i.e. calculation of thd is done on the first 5 harmonics). 13.1.2.4 signal-to-noise ratio (s/n) the ratio of the output signal power to the noise power, excluding the harmonics and the dc com ponent. s/n db ?? 10 p signal p noise ---------------- - log = (5) 13.1.2.5 spurious free dynamic range (sfdr) the number sfdr specifies available signal range as the spectral distance between the a mplitude of the fundamental and the amplit ude of the largest spurious (harmonic and non-harmonic), excluding dc component. sfdr db ?? 20 ? 1 max s ?? ----------------- - log = (6)
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 27 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 13.1.3 intermodulation distortion 13.1.3.1 spectral analysis (dual-tone) imd3 014aaa441 f s /2 measured output range (mhz) magnitude fig 27. spectral analysis (dual-tone) from a dual-tone input sinusoid (f t1 and f t2 , these frequencies being chosen according to the coherence criterion), the intermodulation distortion products imd2 and imd3 (respectively, 2nd and 3rd-order components) are defined, as follows. 13.1.3.2 imd2 (imd3) the ratio of the rms value of either tone to the rms value of the worst second (third) o rder intermodulation product. the total imd is given by: imd db ?? 10 p intermod p signal ----------------------- log = where, p intermod a im 2 f t1 f t2 ? ?? a im 2 f t1 f t2 + ?? a im 2 f t1 2f t2 ? ?? a im 2 f t1 2f t2 + ?? a im 2 2f t1 f t2 ? ?? a im 2 2f t1 f t2 + ?? + + ++ ? = p signal a 2 f t1 ?? a 2 f t2 ?? += and a im 2 f t ?? is the power in the intermodulation component at frequency f t . 13.1.4 noise power ratio (npr) when using a notch-filtered broadband white-noise generator as the input to the adc under test, the npr is defined as the ratio of the average out-of-notch to the in-notch power spectral density magnitudes for the fft spectrum of the adc output sample set.
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 28 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 14. package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 97-08-01 03-02-25 d (1) (1)(1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.1 fig 28. package outline sot307-2 (qfp44)
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 29 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 15. revision history table 11. revision history document id release date data sheet status change notice supersedes adc1006s055_070_3 20120702 product data sheet - adc1006s055_070_2 adc1006s055_070_2 20080812 product data sheet - adc1006s055_070_1 modifications: ? corrections made to titles in figure 13 and 14. ? corrections made to note in figure 4. adc1006s055_070_1 20080611 product data sheet - - 16. contact information for more information or sales office addresses, please visit: http://www.idt.com
adc1006s055_070_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 30 of 30 integrated device technology adc1006s055/070 single 10 bits adc, up to 55 mhz or 70 mhz 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 ordering information . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 thermal characteristics . . . . . . . . . . . . . . . . . . 6 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 11 additional inform ation relating to table 6 . . . 12 12 application information. . . . . . . . . . . . . . . . . . 19 12.1 application diagrams . . . . . . . . . . . . . . . . . . . 19 12.2 demonstration board . . . . . . . . . . . . . . . . . . . 21 12.3 alternative parts . . . . . . . . . . . . . . . . . . . . . . . 24 12.4 recommended companion chip . . . . . . . . . . . 24 13 support information . . . . . . . . . . . . . . . . . . . . 25 13.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13.1.1 non-linearities . . . . . . . . . . . . . . . . . . . . . . . . 25 13.1.1.1 integral non-linearity (inl ) . . . . . . . . . . . . . . 25 13.1.1.2 differential non-linearity (dnl) . . . . . . . . . . . 25 13.1.2 dynamic parameters (singl e tone) . . . . . . . . . 25 13.1.2.1 signal-to-noise and distortion (sinad) . . . . 26 13.1.2.2 effective number of bits (enob) . . . . . . . . . 26 13.1.2.3 total harmonic distortion (thd) . . . . . . . . . . 26 13.1.2.4 signal-to-noise ratio (s/n) . . . . . . . . . . . . . . . 26 13.1.2.5 spurious free dynamic range (sfdr). . . . . 26 13.1.3 intermodulation distortion. . . . . . . . . . . . . . . . 27 13.1.3.1 spectral analysis (dual-tone) . . . . . . . . . . . . . 27 13.1.3.2 imd2 (imd3) . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.1.4 noise power ratio (npr) . . . . . . . . . . . . . . . 27 14 package outline. . . . . . . . . . . . . . . . . . . . . . . . 28 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 29 16 contact information . . . . . . . . . . . . . . . . . . . . 29 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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